Title :
Improved latency insertion method for simulation of large networks with low latency
Author :
Gao, Ran ; Schutt-Ainé, J.E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
In this work, a block processing method is introduced to increase the speed of the latency insertion method while maintaining stability. By partitioning a large network into blocks, the simulation speed increases and memory usage is reduced significantly.
Keywords :
circuit simulation; circuit stability; integrated circuit design; logic partitioning; block processing method; integrated circuit design; large networks; latency insertion method; memory usage; network block partitioning; simulation; simulation speed; stability; Capacitors; Circuit simulation; Circuit stability; Computational modeling; Delay; Equations; Inductors; Niobium; Stability criteria; Voltage;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on
Conference_Location :
Monterey, CA, USA
Print_ISBN :
0-7803-7451-7
DOI :
10.1109/EPEP.2002.1057878
