DocumentCode :
2505985
Title :
Wafer level encapsulation for system in package generation
Author :
Braun, T. ; Becker, K.-F. ; Koch, M. ; Bader, V. ; Manessis, D. ; Neumann, A. ; Ostmann, A. ; Aschenbrenner, R. ; Reichl, H.
Author_Institution :
Fraunhofer Inst. for Reliability & Microintegration, Berlin, Germany
fYear :
2003
fDate :
8-11 May 2003
Firstpage :
505
Lastpage :
511
Abstract :
Within this paper, encapsulation technologies as transfer molding and printing have been investigated; focusing on the feasibility of reliable wafer encapsulation and the suitability of current materials. For these processes the potential of 3D structuring during the encapsulation has been evaluated. An electroless metallization process and laser techniques for structuring the metallization layer have been investigated for reliable interconnections. Summarized this paper presents the process development and feasibility of wafer level encapsulation technologies for SiP solutions.
Keywords :
chip scale packaging; encapsulation; interconnections; laser materials processing; metallisation; reliability; transfer moulding; 3D structuring; bumped wafers; chip scale packaging; electroless metallization process; encapsulant layer; interconnections; laser materials processing; reliability; system in package generation; wafer level SiP encapsulation; wafer level encapsulation; wafer level liquid encapsulation; wafer level molding; wafer level printing; Assembly; Chip scale packaging; Encapsulation; Flip chip; Metallization; Printing; Protection; Surface-mount technology; Wafer scale integration; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Technology: Integrated Management of Electronic Materials Production, 2003. 26th International Spring Seminar on
Print_ISBN :
0-7803-8002-9
Type :
conf
DOI :
10.1109/ISSE.2003.1260582
Filename :
1260582
Link To Document :
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