Title :
Analysis and design of critically damped power distribution network for high performance microprocessor systems
Author_Institution :
Somerset Design Center, Motorola Corp., Austin, TX, USA
Abstract :
Based on the design oriented time domain and frequency analysis of the lumped model of power distribution network (PDN) involving high performance microprocessor core, packaging, PCB and power source, this paper presents simple design equations to realize the critically damped transient response at the microprocessor load. In order to realize the critically damped PDN with flat output impedance magnitude, a systematic method of sizing the decoupling capacitors to be used in the distributed model of PDN is described. Simulation results are presented, verifying the validity of the systematic design methodology.
Keywords :
frequency-domain analysis; integrated circuit packaging; microcomputers; microprocessor chips; network analysis; network synthesis; power supply circuits; time-domain analysis; transient response; PCB; critically damped power distribution network; critically damped transient response; decoupling capacitor sizing; design equations; design methodology; design oriented frequency domain analysis; design oriented time domain analysis; distributed model; flat output impedance magnitude; high performance microprocessor systems; lumped model; packaging; power source; Equations; Frequency domain analysis; Impedance; Microprocessors; Packaging; Performance analysis; Power system modeling; Power systems; Time domain analysis; Transient response;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on
Conference_Location :
Monterey, CA, USA
Print_ISBN :
0-7803-7451-7
DOI :
10.1109/EPEP.2002.1057911
