Design and modeling of a 3.2 Gbps/pair memory channel

With the rapid advance of silicon process technology, it is now possible to design I/O circuits that operate at multi-gigabit data rates. Rambus´s next generation memory interface technology, code-named Yellowstone, utilizes bi-directional low-swing Differential Rambus Signaling Level (DRSL) with a data transfer rate starting at 3.2 Gbps/pair and scalable to 6.4 Gbps/pair. This paper describes the design and modeling methodology used to develop the Yellowstone memory channel with conventional interconnect technologies. First, the advantages of point-to-point differential signaling are discussed. Then, the design issues associated with low-cost conventional printed circuit boards (PCBs) and packages are described. This is followed by a discussion of the modeling issues associated with high data-rate channel design. A design and modeling methodology is proposed to ensure the robust operation of the Yellowstone memory channel. Finally, to illustrate the validity of the proposed modeling methodology, channel models are correlated with actual hardware at both component and system level in both time and frequency domains.