DocumentCode :
2506278
Title :
40 Gbit/s "fish ladder" signal path and connectorized signal path in ceramic and organic packages for OC768 applications
Author :
Pillai, Edward R.
Author_Institution :
IBM Corp., Hopewell Junction, NY, USA
fYear :
2002
fDate :
21-23 Oct. 2002
Firstpage :
239
Lastpage :
242
Abstract :
IBM is providing robust packaging solutions for high speed networking chips utilizing Silicon Germanium (SiGe) and CMOS technology. Recently, while still using current packaging design ground rules needed to yield a manufacturable product, a novel "fish ladder" transmission line structure that exits through the 2nd level Package Ball Grid Array (BGA) onto a Printed Circuit Board (PCB) was introduced into the package. The benefit afforded by this structure allows the system designer the ability to route high speed signal traces directly through to the PCB where highly reliable Surface Mount Technology (SMT) connectors can be used, thereby eliminating the need for more costly and assembly intensive techniques for connectors on the package. The "fish ladder" for the first time can support 40 Gbit/s and 50 Gbit/s transmission speeds. Herein is described the "fish ladder" structure, the electrical modeling of the structure up to 40 GHz in both IBM\´s alumina ceramic and SLC/spl trade/ (Surface Laminar Circuit) organic package. Also the S parameter measurement of the assembled package up to 45 GHz demonstrating the performance is included.
Keywords :
S-parameters; ball grid arrays; ceramic packaging; coplanar waveguides; digital integrated circuits; electric connectors; high-speed integrated circuits; integrated circuit interconnections; integrated circuit packaging; printed circuits; surface mount technology; 40 Gbit/s; 45 GHz; 50 Gbit/s; 65 GHz; Al/sub 2/O/sub 3/; BGA; CMOS technology chips; CPW transmission line; IBM; OC768 applications; PCB; SLC organic package; SMT connectors; Si; SiGe; SiGe technology chips; alumina ceramic package; ball grid array; connectorized signal path; fish ladder transmission line structure; high speed networking chips; high speed signal traces; multilayer package; mux/demux chip application; printed circuit board; robust packaging solutions; surface laminar circuit organic package; surface mount technology; CMOS technology; Ceramics; Connectors; Germanium silicon alloys; High-speed networks; Marine animals; Packaging; Robustness; Silicon germanium; Surface-mount technology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on
Conference_Location :
Monterey, CA, USA
Print_ISBN :
0-7803-7451-7
Type :
conf
DOI :
10.1109/EPEP.2002.1057923
Filename :
1057923
Link To Document :
بازگشت