Impact of power-supply noise on timing in high-frequency microprocessors

Author

Saint-Laurent, Martin ; Swaminathan, Madhavan

Author_Institution

Intel Corp., Austin, TX, USA

fYear

2002

fDate

21-23 Oct. 2002

Firstpage

261

Lastpage

264

Abstract

This paper analyses the impact of power-supply noise on the performance of high-frequency microprocessors. First, a delay model that takes this noise into account is proposed for device-dominated and interconnect-dominated timing paths. Then, realistic values for the model parameters are measured on a 2.53 GHz Pentium/sup /spl reg// 4 microprocessor. These values imply that the power-supply noise present on the system board currently reduces clock frequency by 6.5%. The model suggests that the frequency penalty associated with this power-supply noise will reach 8.0% for the 90-nm technology generation.

Keywords

delay estimation; high-speed integrated circuits; integrated circuit modelling; integrated circuit noise; microprocessor chips; power supply circuits; timing; 2.53 GHz; 90 nm; HF microprocessor timing; Pentium 4 microprocessor; clock frequency; delay model; device-dominated timing paths; high-frequency microprocessors; model parameters; power-supply noise; Clocks; Delay; Frequency; Microprocessors; Noise generators; Noise reduction; Performance analysis; Power system interconnection; Power system modeling; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on

Conference_Location

Monterey, CA, USA

Print_ISBN

0-7803-7451-7

Type

conf

DOI

10.1109/EPEP.2002.1057928

Filename

1057928