DocumentCode :
2506433
Title :
Viterbi Detector Error Rate Analysis and Byte Synchronization System and Method Using an Error Correcting Code (ECC) For PR4 Channel
Author :
Yasuda, Toshiyuki ; Blaum, Mario ; Tang, D.D.
Author_Institution :
IBM Corp.
fYear :
1998
fDate :
6-9 Jan. 1998
Firstpage :
208
Lastpage :
208
Keywords :
Clocks; Decision feedback equalizers; Delay; Detectors; Error analysis; Error correction codes; Linearity; Memory; Synchronization; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
MMM-Intermag Conference, 1998. Abstracts., The 7th Joint
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5118-5
Type :
conf
DOI :
10.1109/INTMAG.1998.742186
Filename :
742186
Link To Document :
بازگشت