Title :
Parallel processor for image segmentation
Author :
Miteran, J. ; Gorria, P. ; Robert, M.
Author_Institution :
Lab. G.E.R.E., Burgundy Univ., Le Creusot, France
Abstract :
We present the architecture of a parallel processor which is suitable for image segmentation. The classification of each pixel is completed using a geometric classification method by stress polytope training, which ensures a high decision speed (100 ns per pixels) and good performances. The decision operator has been integrated in the form of a full custom circuit developed in CMOS 1.2 μm, and the area of silicon obtained is less than 30 mm2
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; digital signal processing chips; image classification; image processing equipment; image segmentation; parallel machines; real-time systems; special purpose computers; ASIC; CMOS; architecture; decision operator; full custom circuit; geometric classification methods; high decision speed; image segmentation; parallel processor; performance; pixel classification; stress polytope training; Application specific integrated circuits; Electronic mail; Image segmentation; Inspection; Integrated circuit manufacture; Laboratories; Manufacturing automation; Productivity; Silicon; Stress;
Conference_Titel :
Electrotechnical Conference, 1994. Proceedings., 7th Mediterranean
Conference_Location :
Antalya
Print_ISBN :
0-7803-1772-6
DOI :
10.1109/MELCON.1994.381083
