A digital bus configuration for a multi-processor system with square pyramid structure

We present a digital bus configuration for multi-processor systems with square pyramid structure. Multi-processor systems with square pyramid structure are closely coupled. Therefore, nodes should not access the same memory location simultaneously. This restriction let us present a simple and efficient bus configuration for interconnecting shared memory units of the multi-processor system. We implement a prototype of a presented system, for real time applications. In addition, for an efficient use of hardware, we implemented a distributed shared memory management software using the message passing technique for the communications between the software modules situated at different nodes