A graded-channel MOS (GCMOS) VLSI technology for low power DSP applications

Graded-Channel MOS (GCMOS) VLSI technology has been developed to meet the growing demand for low power and high performance applications. In this paper, it will be shown that, compared with conventional CMOS, the GCMOS device offers the advantage of significantly higher drive current, capable of lower threshold voltage with improved punchthrough resistance, lower body effect and lower series resistance, thus making it most suitable for applications that require both high performance and low power consumption, such as DSPs. This is demonstrated, for the first time, by much improved low voltage circuit performance of a DSP logic circuit fabricated using a 0.5 μm GCMOS process. At 1.8 V, a 30% speed improvement over CMOS is achieved, and the power-delay product is reduced by 25%