Title :
An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits
Author :
Chatterjee, Amitava ; Nandakumar, Mahalingam ; Chen, Ih-Chin
Author_Institution :
Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
In this paper the effects of technology scaling on the fraction of active power Pa wasted as short-circuit power Ps are studied through SPICE simulations. The accuracy of SPICE is verified against experimental data. SPICE simulations show that lowering VT below 0.1 V can increase Ps/Pa significantly beyond what is expected from increased subthreshold leakage. Ps/Pa is typically higher at higher Vcc but to first order Ps/Pa is determined by signal slew rates and VT. It is shown that the input slew rate is constrained by Ps/Pa at low V T and by performance at higher VT. We show that P s increases with increasing gate sheet resistance. A simple analytical model for this effect is verified against the experimental data and used to determine the gate sheet requirements to maintain Ps/Pa<10% for sub-0.25 μm technologies
Keywords :
CMOS digital integrated circuits; SPICE; circuit analysis computing; electric resistance; fault currents; integrated circuit modelling; integrated circuit technology; short-circuit currents; 0.25 micron; LV static CMOS circuits; SPICE simulations; active power wastage; analytical model; gate sheet resistance; short-circuit current; signal slew rates; sub-quarter micron technologies; subthreshold leakage; technology scaling; threshold voltage; CMOS process; CMOS technology; Energy consumption; Inverters; Low voltage; MOSFET circuits; Power MOSFET; Power dissipation; SPICE; Semiconductor device modeling;
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3571-6
DOI :
10.1109/LPE.1996.547497
