Title :
Ta/sub 2/O/sub 5/ plasma CVD technology for DRAM stacked capacitors
Author :
Numasawa, Y. ; Kamiyama, S. ; Zenke, M. ; Sakamoto, M.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A plasma CVD (chemical vapor deposition) technology was developed that can deposit high-quality Ta/sub 2/O/sub 5/ thin film suitable for the stacked capacitor dielectric film of 64-Mb-DRAM (dynamic RAM) and beyond. Ta/sub 2/O/sub 5/ films as thin as 30 AA SiO/sub 2/ equivalent thickness deposited by this newly developed CVD technology have shown remarkably small leakage current, 1*10/sup -8/ A/m/sup 2/ at 3 MV/cm. The step coverage of the film is also satisfactory. Time-dependent dielectric breakdown (TDDB) measurements have shown that a polysilicon stacked capacitor using the Ta/sub 2/O/sub 5/ film (equivalent to 30 AA SiO/sub 2/) has a reliability corresponding to 3.3 V V/sub cc/ operation for 10 years and more.<>
Keywords :
DRAM chips; VLSI; dielectric thin films; plasma CVD coatings; tantalum compounds; 64 Mbit; DRAM stacked capacitors; Ta/sub 2/O/sub 5/; leakage current; plasma CVD technology; polysilicon stacked capacitor; reliability; stacked capacitor dielectric film; step coverage; time-dependent dielectric breakdown; Capacitors; Chemical technology; Chemical vapor deposition; DRAM chips; Dielectric breakdown; Dielectric films; Dielectric thin films; Leakage current; Plasma chemistry; Sputtering;
Conference_Titel :
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1989.74224
