DocumentCode
2507492
Title
Power consumption reduction scheme focusing on the Depth of Speculative Execution
Author
Oshima, Hideki ; Kobayashi, Ryotaro ; Shimura, Kazuki ; Shimada, Toshio
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Nagoya Univ., Nagoya
fYear
2008
fDate
8-11 July 2008
Firstpage
207
Lastpage
212
Abstract
A mechanism is proposed that reduces power consumption, and which focuses on the speculative execution depth (SED). SED is the number of branch instructions whose results are not yet known in the processor. The mechanism controls the SED depending on the current workload. The evaluation results show that the proposed scheme can reduce power consumption by 10.8-41.0% when the target throughput ranges from 60-90%, and suppress the average error margin with the target throughput to 1.0% or less.
Keywords
microprocessor chips; power consumption reduction scheme; speculative execution depth; Clocks; Computer science; Dynamic voltage scaling; Energy consumption; Frequency; Microprocessors; Process design; Threshold voltage; Throughput; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer and Information Technology, 2008. CIT 2008. 8th IEEE International Conference on
Conference_Location
Sydney, NSW
Print_ISBN
978-1-4244-2357-6
Electronic_ISBN
978-1-4244-2358-3
Type
conf
DOI
10.1109/CIT.2008.4594675
Filename
4594675
Link To Document