Title :
Implementation of systolic multipliers and digital filters via signal flow-graph transformations
Author :
Pekmestzi, K.Z. ; Caraiscos, C.G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Greece
Abstract :
Massive insertion of delay elements in a one-way signal flow-graph of an FIR digital filter, and/or proper transfer of delay elements between edges in a two-way signal flow-graph lead to systolic arrays for the implementation of a serial-parallel multiplier, a bit-parallel multiplier, and an FIR digital filter. All of them are of the merged type and exhibit lower latency than existing ones, without any increase in throughput or circuitry
Keywords :
FIR filters; digital filters; multiplying circuits; pipeline arithmetic; signal flow graphs; systolic arrays; FIR digital filter; bit-parallel multiplier; delay elements; digital filters; one-way signal flow-graph; serial-parallel multiplier; signal flow-graph transformations; systolic multipliers; throughput; two-way signal flow-graph; Circuits; Delay; Digital filters; Finite impulse response filter; Interleaved codes; Merging; Pipelines; Systolic arrays; Throughput; Transfer functions;
Conference_Titel :
Electrotechnical Conference, 1994. Proceedings., 7th Mediterranean
Conference_Location :
Antalya
Print_ISBN :
0-7803-1772-6
DOI :
10.1109/MELCON.1994.381133
