Efficient multiplierless channel filters for multi-standard SDR

This paper investigates the design of very low complexity multiplierless linear phase FIR filters for use in the channelizer of multi-standard software defined radios. A technique for reducing the hardware complexity of linear phase FIR digital filters which minimizes the adder depth and the number of adders in the multiplier block is introduced and is used to implement a multistage, multi-standard decimating filter. The design reuses components for different communications standards and is thus ideal for use in systems which support dynamic reconfiguration.