Array processor featuring an effective FIFO-based data stream management

In array processors, data I/O management is the key to realizing high-speed matrix operations that are often required in signal and image processing. In this paper, we propose an array processor utilizing an effective data I/O mechanism featuring external FIFOs. The FIFOs are used to buffer initial matrix data and partially processed results. Therefore, if all required data are stored in the FIFOs, matrix operations, including the algorithm to solve the Algebraic Path Problem (APP), can be performed without any data I/Os. In addition, we can eliminate register files from the processing elements (PEs) if we construct the PE array by controlling the external FIFOs systematically and transferring the data from (to) the FIFOs to (from) the PE array. This enables us to simplify each PE structure and realize a large array processor with limited hardware resources. Here, the FIFOs themselves can be easily realized using conventional discrete FIFO or memory chips.