Title :
A novel, low-power array multiplier architecture
Author :
Bajaj, Ronak ; Chhabra, Saransh ; Veeramachaneni, Sreehari ; Srinivas, M.B.
Author_Institution :
Int. Inst. of Inf. Technol.-Hyderabad, Hyderabad, India
Abstract :
Low power parallel array multiplier is proposed for both unsigned and two´s complement signed multiplication. Modified Baugh-Wooley multiplier is further modified and if input numbers are not in two´s complement form, proposed method makes the calculation of two´s complement of the number redundant, thus reducing delay. Also power consumption has been found to be less than that of modified Baugh-Wooley multiplier.
Keywords :
low-power electronics; multiplying circuits; low-power array multiplier architecture; modified Baugh-Wooley multiplier; Algorithm design and analysis; Arithmetic; Delay; Design optimization; Digital circuits; Digital signal processing; Electronic mail; Energy consumption; Microprocessors; Power dissipation;
Conference_Titel :
Communications and Information Technology, 2009. ISCIT 2009. 9th International Symposium on
Conference_Location :
Icheon
Print_ISBN :
978-1-4244-4521-9
Electronic_ISBN :
978-1-4244-4522-6
DOI :
10.1109/ISCIT.2009.5341273
