Title :
Characterization of die stresses in microprocessor packages subjected to thermal cycling
Author :
Roberts, Jordan ; Hussain, Safina ; Suhling, Jeffrey C. ; Jaeger, Richard C. ; Lall, Pradeep
Author_Institution :
Dept. of Mech. Eng., Auburn Univ., Auburn, AL, USA
fDate :
May 30 2012-June 1 2012
Abstract :
In this work, we have used test chips containing piezoresistive sensors to characterize the in-situ die surface stress evolution during thermal cycling of flip chip ceramic ball grid array (FC-CBGA) components suitable for microprocessor packaging. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the individual test chip wafers. After every packaging step (flip chip solder ball reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A package carrier was developed to allow measurement of the die stresses in the FC-CBGA components subjected to thermal cycling loads without inducing any additional mechanical loadings. Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recor- ed continuously. From the resistance data, the stresses at each site were calculated and plotted versus time.
Keywords :
ball grid arrays; ceramic packaging; flip-chip devices; integrated circuit interconnections; integrated circuit measurement; integrated circuit packaging; microprocessor chips; piezoelectric transducers; solders; stress analysis; FC-CBGA components; Si; adhesive cure; data acquisition hardware; die device surface; die stresses characterization; flip chip ceramic ball grid array; flip chip solder ball reflow; high CTE ceramic chip carriers; in-situ die surface stress evolution; in-situ measurements; lead free solder interconnects; lid attachment; mechanical loadings; microprocessor packages; package carrier; piezoresistive sensors; sensor resistances; silicon test chips; temperature 0 C to 100 C; thermal cycling loads; three-dimensional stress state; time 10 min; time 40 min; transient die stress variations; underfill dispense-cure; Ceramics; Electrical resistance measurement; Semiconductor device measurement; Sensors; Stress; Stress measurement; Temperature measurement;
Conference_Titel :
Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2012 13th IEEE Intersociety Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-9533-7
Electronic_ISBN :
1087-9870
DOI :
10.1109/ITHERM.2012.6231535