Cell level thermal placement in 3D ICs

Thermal issues are playing a dominant role in today´s high performance VLSI design. On-chip power density has become an important parameter during the physical design phase. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Moreover, 3D chips have significantly larger power densities than their 2D counterparts. In this paper, we consider the placement of standard cells and gate arrays (modules) under thermal considerations. Our contribution includes a novel algorithm for placement of the gates or cells in the different active layers of a 3D IC to ensure (i) an uniform distribution of temperatures of the modules in each active layers, (ii) lowest possible value of the maximum temperatures of each of the active layers, and (iii) a temperature gradient of the maximum temperatures of the layers in a non-increasing manner from bottom layer to top layer to ensure efficient heat dissipation in the face-to-back bonding structure. Experimental results on randomly generated and standard benchmark instances are quite encouraging.