Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices

This paper presents an accurate model for the evaluation of the CMOS short-circuit power dissipation for short-channel devices, on the basis of a CMOS inverter. The improvement of the proposed approach against previous works is due to the new derived, accurate, analytical expressions for the inverter output waveform which include for the first time the influences of both transistor currents, and the gate-to-drain coupling capacitance. The results produced by she suggested model show good agreement with SPICE simulations