DocumentCode
2508612
Title
High level design validation: current practices and future directions
Author
Ghosh, Indradeep ; Prasad, Mukul ; Mukherjee, Rajarshi ; Fujita, Masahiro
Author_Institution
Fujitsu Labs. of America, Inc., Sunnyvale, CA, USA
fYear
2004
fDate
2004
Firstpage
9
Lastpage
11
Abstract
This paper describes about the increasing complexity of VLSI design, time to market pressures. The two major paradigms to address the difficulties currently being faced by industry are: (1) the use of higher levels of design abstraction and (2) efficient and seamless design reuse. Current industrial practices and academic research in design verification and validation are also discussed.
Keywords
VLSI; formal verification; integrated circuit design; integrated circuit modelling; specification languages; VLSI design; design reuse; high level design abstraction; high level design validation; Automatic test pattern generation; Automatic testing; Design engineering; Electronics industry; Hardware design languages; Industrial electronics; Laboratories; Time to market; Unified modeling language; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN
0-7695-2072-3
Type
conf
DOI
10.1109/ICVD.2004.1260892
Filename
1260892
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