New systems for fabrication of wafer scale interconnections in multichip packages

Processing tools for improving the yield in the fabrication of wafer-scale interconnections for multichip packages are discussed. Tools for deposition and etching of dielectrics and for metal deposition are covered. Efforts to introduce parylene dielectric films, which have lower curing temperatures than polyimide, are discussed. The need to avoid high-temperature processing steps in metal film production is stressed. The use of focused electron and ion beam repair strategies to cope with residual faults in a high-yield WSI lift-off process is explored.<>