DocumentCode
2509182
Title
Low-power frequency multiplier with one cycle lock-in time and 100 ppm frequency resolution, for system power-management
Author
Fried, Rafael ; Azmanov, Ziv
Author_Institution
Dept. of Electr. Eng., Swiss Federal Inst. of Technol., Lausanne, Switzerland
fYear
1996
fDate
12-14 Aug 1996
Firstpage
281
Lastpage
284
Abstract
A low-power Frequency Multiplier (FMUL) with 100 ppm frequency resolution, +/-100 ps jitter, and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a reference frequency of 32,768 Hz, for advanced power management both at a device level and at a system level. The FMUL is implemented in a standard digital CMOS process and its area is 0.5 mm2@0.8 μm
Keywords
CMOS digital integrated circuits; clocks; frequency multipliers; jitter; power integrated circuits; 0.8 micron; 100 MHz; clock frequency generation; digital CMOS process; frequency resolution; jitter; low-power frequency multiplier; one cycle lock-in time; system power-management; Batteries; Clocks; Control systems; Energy management; Frequency; Home appliances; Personal communication networks; Phase locked loops; Power system management; Thermal management;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-3571-6
Type
conf
DOI
10.1109/LPE.1996.547523
Filename
547523
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