Title :
Low-power frequency multiplier with one cycle lock-in time and 100 ppm frequency resolution, for system power-management
Author :
Fried, Rafael ; Azmanov, Ziv
Author_Institution :
Dept. of Electr. Eng., Swiss Federal Inst. of Technol., Lausanne, Switzerland
Abstract :
A low-power Frequency Multiplier (FMUL) with 100 ppm frequency resolution, +/-100 ps jitter, and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a reference frequency of 32,768 Hz, for advanced power management both at a device level and at a system level. The FMUL is implemented in a standard digital CMOS process and its area is 0.5 mm2@0.8 μm
Keywords :
CMOS digital integrated circuits; clocks; frequency multipliers; jitter; power integrated circuits; 0.8 micron; 100 MHz; clock frequency generation; digital CMOS process; frequency resolution; jitter; low-power frequency multiplier; one cycle lock-in time; system power-management; Batteries; Clocks; Control systems; Energy management; Frequency; Home appliances; Personal communication networks; Phase locked loops; Power system management; Thermal management;
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3571-6
DOI :
10.1109/LPE.1996.547523
