Title :
Logic synthesis using power-sensitive Don´t Care sets
Author :
Lennard, Christopher K. ; Buch, Premal ; Newton, A. Richard
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The Boolean space spanned by the primary input vectors of a combinational function may contain a large variance in minterm probabilities. By partitioning the Don´t Care set into regions strongly and weakly influential upon switching activity we exploit this variance to bias area-optimization rewards reduced power dissipation. Experimental results indicate that our method can reduce power dissipation of a combinational CMOS circuit with no penalty in area
Keywords :
Boolean algebra; CMOS logic circuits; combinational circuits; logic partitioning; minimisation of switching nets; Boolean space; bias area optimization; combinational CMOS circuit; don´t care sets; logic synthesis; minterm probabilities; partitioning; power dissipation; switching; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Energy consumption; Power dissipation; Probability distribution; Semiconductor device modeling; Space exploration; Switching circuits;
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3571-6
DOI :
10.1109/LPE.1996.547526
