Logic synthesis using power-sensitive Don´t Care sets

The Boolean space spanned by the primary input vectors of a combinational function may contain a large variance in minterm probabilities. By partitioning the Don´t Care set into regions strongly and weakly influential upon switching activity we exploit this variance to bias area-optimization rewards reduced power dissipation. Experimental results indicate that our method can reduce power dissipation of a combinational CMOS circuit with no penalty in area