Title :
Novel ultra low-voltage and high-speed CMOS pass transistor logic
Author :
Berg, Y. ; Azadmehr, M.
Author_Institution :
Inst. of Technol., Vestfold Univ. Coll., Horten, Norway
Abstract :
In this paper we present a novel CMOS pass transistor logic style for ultra low-voltage and high speed digital applications. The circuits presented offer more than 90% delay reduction compared to conventional CMOS for supply voltages less than 400mV. Differential AND and NAND pass transistor gates presented and compared to complementary pass transistor logic CPL. Simulated data obtained by the H spice simulation and relevant for 90nm TSMC process are provided.
Keywords :
CMOS logic circuits; logic gates; transistor circuits; H spice simulation; NAND pass transistor gates; complementary pass transistor logic CPL; delay reduction; high speed CMOS pass transistor logic; high speed digital application; supply voltage; ultra low-voltage CMOS pass transistor logic; CMOS integrated circuits; Capacitance; Delay; Logic gates; MOS devices; Threshold voltage; Transistors;
Conference_Titel :
Faible Tension Faible Consommation (FTFC), 2012 IEEE
Conference_Location :
Paris
Print_ISBN :
978-1-4673-0822-9
DOI :
10.1109/FTFC.2012.6231719
