Title :
Controller re-specification to minimize switching activity in controller/data path circuits
Author :
Raghunathan, Anand ; Dey, Sujit ; Jha, Niraj K. ; Wakabayashi, Kazutoshi
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Abstract :
This paper proposes a controller-based technique for minimizing switching activity in controller/data path circuits. Though the control signals in a register transfer level (RTL) implementation are fully specified, they can be respecified under certain states/conditions when the data path components that they control need not be active. Unlike techniques that insert extra circuitry like transparent latches, controller re-specification is a low-overhead technique that merely reconfigures existing multiplexer networks and functional units to minimize activity in the data path. Hence, it is well suited to control-flow intensive designs, where power consumption in multiplexer networks forms a major component of the total power consumption. Our controller re-specification algorithm consists of constructing an activity graph for each data path component, identifying conditions under which the component need not be active, and re-labeling the activity graph resulting in re-specification of the corresponding control expressions. Application of the proposed technique to several RTL circuits demonstrated the ability to reduce the total (controller+data path) power consumption by up to 51.8% compared to the initial area-optimized implementations, with nominal area and delay overheads
Keywords :
CMOS logic circuits; delays; graph theory; logic CAD; CMOS logic; activity graph; control-flow intensive designs; controller re-specification; controller/data path circuits; delay overhead; functional units; low-overhead technique; multiplexer networks; nominal area overhead; power consumption; register transfer level implementation; switching activity; Automatic control; CMOS logic circuits; Energy consumption; Feeds; Latches; Multiplexing; National electric code; Reconfigurable logic; Switching circuits; Tree graphs;
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3571-6
DOI :
10.1109/LPE.1996.547528