Low energy switch block for FPGAs

We propose a new energy efficient method of designing switch blocks inside FPGAs using novel variations of the Dual Threshold CMOS (DTMOS) based switches instead of the conventional NMOS pass transistor or tri-state buffer based switches. By intelligently sharing the extra transistor needed for using DTMOS based switches, the area overhead is kept to a minimum. Sleep transistors are used to reduce sub-threshold leakage. Using our new, novel design, we obtain a 16% improvement in the power-delay product during the active mode per switch and a factor of 20 improvement in the stand-by mode, over conventional approaches. Extensive simulation results over benchmark circuits in CMOS 0.13μ are presented to illustrate the superiority of the proposed techniques. Since the proposed techniques target the switches and multiplexers which are present in large numbers on FPGAs, the overall improvement in the power-delay product is significant for an application implemented on a FPGA having the proposed features.