Leakage reduction techniques in a 0.13 um SRAM cell

SRAM standby leakage is very becoming critical with technology scaling to meet the industry´s demanding low power requirements. This paper discusses some of the leakage reduction techniques in a 0.13 um SRAM cell in a standard foundry process. Varying the cell bias voltages (VDD, VSS, well biases, bit-line pre-charge, and wordline off) to different standby levels helps achieve reduced leakage. Variation of these bias voltages by 0.3 v from normal voltage levels reduces the leakage to 10 pA/Cell at room temperature. The VDD and bit-line pre-charge levels need to be restored to at least 95% of the normal level before an active cycle for reliable noise margin. Depending on the bias voltage (VDD or VSS or both) variation, the access time and the static noise margin will be affected. This paper studies the details of critical SRAM cell parameters for different bias voltages variations to reduce standby leakage and their impact to the overall design.