Novel differential sensing for 0.5-V sub-32-nm UTBB FD-SOI SRAMs

Author

Shaik, K.A. ; Amara, A. ; Flatresse, P. ; Giraud, B. ; Noel, J.P. ; Prayer, B.P. ; Nagchoudhuri, D.

Author_Institution

Inst. Super. d´´Electron. de Paris (ISEP), Paris, France

fYear

2012

fDate

6-8 June 2012

Firstpage

1

Lastpage

4

Abstract

A novel differential sensing with gated diode (GD) based bit-line (BL) voltage difference boosting, is proposed for sub-32-nm SRAMs. The non-linear capacitance of GD with the generated current difference conditionally amplifies a BL differential signal in short transition time. The amplification is maximized by the double-gate structure of UTBB FD-SOI used for GD. The small source capacitance of the GD enables fast GD-driving. Simulations of a sub-32-nm 32kb memory with the scheme have shown 3.8 times improvement in performance with read access time of 2.6ns at 0.5V supply voltage.

Keywords

SRAM chips; amplification; capacitance; low-power electronics; power supply circuits; silicon-on-insulator; BL differential signal; BL voltage difference boosting; GD based bit-line voltage difference boosting; GD-driving; UTBB FD-SOI SRAM; amplification; differential sensing; double-gate structure; gated diode; generated current difference; nonlinear capacitance; read access time; short transition time; size 32 nm; source capacitance; storage capacity 32 Kbit; supply voltage; time 2.6 ns; voltage 0.5 V; Boosting; Capacitance; Logic gates; Random access memory; Sensors; Transistors; Voltage control; Bit-line voltage difference boosting; Differential sensing; FD-SOI SRAM; Gated-diode;

fLanguage

English

Publisher

ieee

Conference_Titel

Faible Tension Faible Consommation (FTFC), 2012 IEEE

Conference_Location

Paris

Print_ISBN

978-1-4673-0822-9

Type

conf

DOI

10.1109/FTFC.2012.6231726

Filename

6231726