Application of a parasitic aware model to optimize an RF energy scavenging circuit fabricated in 130 nm CMOS

Design parameters, including transistor width and number of stacked stages, contribute to the efficiency of RF scavenging systems. This leads to a large design space and, as a result, designing optimal RF scavenging circuits for a given performance requirement is a difficult problem. This work presents an analytical model based on the physical design parameters of the power matched Villard voltage doubler. This model is successfully used to determine the optimal design of an RF energy scavenging circuit fabricated in a 130 nm IBM process.