New high-speed and low-power radix-2r multiplication algorithms

In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (N/r), but also eliminates the need of pre-computing odd multiples of the multiplicand in higher radix (r≥3) multiplication. Based on a mathematical proof that any higher radix-2^r can be recursively derived from a combination of two or a number of lower radices, a series of generalized radix-2^r multipliers are generated by means of primary radices: 2¹, 2², 2⁵, and 2⁸. A variety of higher-radix (2³-2³²) two´s complement 64×64 bit serial/parallel multipliers are implemented on Virtex-6 FPGA and characterized in terms of multiply-time, energy consumption per multiply-operation, and area occupation for r value varying from 2 to 64. Compared to a recent published algorithm, savings of 21%, 53%, 105% are respectively obtained in terms of speed, power, and area.