A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI)

A novel quasi-adiabatic, precharge-evaluate logic family, Dynamic Adiabatic MOS (DAMOS), is proposed. Wave-pipelined DAMOS inverter chain datapaths in a 0.25 μm, 2.5 V CMOS device technology are shown to successfully recycle 73% and 89% of the energy available from the power-clock in high-performance (200 MHz) and fixed-throughput (10 MHz) applications, respectively. DAMOS offers significantly smaller energy dissipation and device count per gate compared to previously reported dynamic quasi-adiabatic (but irreversible) logic families. Computational energy and power of a wave-pipelined DAMOS inverter chain (excluding dissipations in the power-clock generator) are 83% to 93% smaller than that consumed by its conventional Domino CMOS counterpart (excluding dissipations in the clock drivers) at identical operational throughputs. In addition, DAMOS provides one to three orders of magnitude reduction in peak power compared to Domino logic, indicating significant relaxation of electrical stress in both devices and interconnections. Novel high-efficiency power-clock generation techniques must be pursued to fully exploit the large computational energy efficiency of quasi-adiabatic logic in general and of DAMOS in particular