Title :
Performance comparison of channel coding for 60GHz SC-PHY and a multigigabit Viterbi decoder
Author :
Gao, Bo ; Xiao, Zhenyu ; Zhang, Changming ; Su, Li ; Jin, Depeng ; Zeng, Lieguang
Author_Institution :
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Abstract :
In this paper, we make a performance comparison between convolutional(171,133) codes (CC), concatenated RS(255,239)-convolutional(171,133) codes (RS-CC) and LDPC(672,336) based on 60GHz single carrier physical layer (SC-PHY). With the effect of phase noise and non-linear distortion of power amplifier (NLPA) taken into account, RS-CC reveals higher robustness against the effect over LDPC, and it has the better bit-error rate performance than LDPC. Over and above, a forward independent sliding-block architecture for Viterbi decoders (FISB-VD) is proposed to achieve multigigabit inner-CC decoding of the RS-CC. A 16-parallel FISB-VD has been implemented in a Xilinx Virtex-6 FPGA device, of which the maximum decoding rate can be up to 3.2 Gbps.
Keywords :
Reed-Solomon codes; Viterbi decoding; channel coding; concatenated codes; convolutional codes; field programmable gate arrays; nonlinear distortion; parity check codes; personal area networks; phase noise; power amplifiers; wireless LAN; Reed-Solomon convolutional codes; SC-PHY; Xilinx Virtex-6 FPGA device; bit error rate; channel coding; concatenated codes; frequency 60 GHz; low density parity check codes; multigigabit Viterbi decoder; nonlinear distortion; performance comparison; phase noise; power amplifier; single carrier physical layer; sliding-block architecture; Bit error rate; Channel coding; Decoding; Measurement; Parity check codes; Wireless personal area networks; 60GHz; LDPC; Viterbi decoders; concatenated RS-convolutional codes; single carrier;
Conference_Titel :
Computational Problem-Solving (ICCP), 2011 International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4577-0602-8
Electronic_ISBN :
978-1-4577-0601-1
DOI :
10.1109/ICCPS.2011.6092169
