Assertion based verification using HDVL

Over the past several years verification of large designs are becoming more and more complex-both in terms of the maintaining the code size and in keeping parity between the specification written in English; design written in HDL (typically Verilog/VHDL) and the verification models-written in HDL or some proprietary verification language. To alleviate this problem, Accellera has come up with the proposal for standardizing an HDVL-a single language that caters to all the needs for Design (as an HDL) as well as Verification (as an HVL-Hardware Verification Language). System Verilog standard where the user can model and verify the correctness of the designs using a unified language whose syntax and semantics is already proven and tested in the industry is being projected as a candidate HDVL. SystemVerilog is a set of major enhancements to the Verilog 2001 standard and these enhancements are taken from existing industry standard languages and paradigms including Superlog, PSL-Sugar, OVA and OVL. In this paper we present an overview of the Assertion based Verification methodology in general and explain, with suitable examples, how can one benefit from using an HDVL for the combined purpose of design as well as verification. It attempts to set the right expectations for an engineer from an HDVL and also illustrates the power of the new paradigm.