Design and implementation of a parallel Verilog simulator: PVSim

Parallel HDL simulation is an efficient method to accelerate the verification process of large complex VLSI system design. This paper presents a parallel Verilog simulator-PVSim, which bases on optimistic asynchronous parallel simulation algorithm and MPI library. A new module-based simulation component mapping method is proposed. And an efficient module-based partition algorithm combined with pre-simulation partition algorithm is adopted. This paper introduces the architecture of PVSim, the Verilog component mapping techniques, the distributed simulation cycle arrangement and the circuit partition algorithm in detail. Experimental results show that PVSim can get promising speedup, as well as distributed workload and communication cost across processors.