Low power optimization for a 40nm RFCMOS wireless connectivity chip

Author

Lixin, Liang ; Gang, Guo ; Royannez, Philippe

Author_Institution

Connectivity - SoC, ST-Ericsson, Singapore, Singapore

fYear

2012

fDate

6-8 June 2012

Firstpage

1

Lastpage

4

Abstract

In this paper we present the power optimization of a GNSS, Bluetooth, FM radio combo SoC for smartphones and tablet devices. The optimization ranges from architectural level, clock management level and RTL level. The techniques of power state and power control, clock gating, clock distribution, operand isolation and logic grouping have been tailored to the specific needs of wireless combo SoC. The techniques and optimization has been proven on fully functional 40nm RFCMOS silicon and shows up to 20% power reduction vs. non-optimized version.

Keywords

Bluetooth; CMOS integrated circuits; logic design; low-power electronics; satellite navigation; system-on-chip; Bluetooth; FM radio combo SoC; GNSS; RFCMOS wireless connectivity chip; RTL level; architectural level; clock distribution; clock gating; clock management level; logic grouping; low power optimization; operand isolation; power control; power reduction; power state; size 40 nm; smartphone; tablet device; Clocks; Frequency synchronization; Hardware; Logic gates; Optimization; Synchronization; System-on-a-chip; SoC; clock gating; clock tree; low-power; operand isolation; power optimization;

fLanguage

English

Publisher

ieee

Conference_Titel

Faible Tension Faible Consommation (FTFC), 2012 IEEE

Conference_Location

Paris

Print_ISBN

978-1-4673-0822-9

Type

conf

DOI

10.1109/FTFC.2012.6231744

Filename

6231744