• DocumentCode
    2509906
  • Title

    An efficient verification of quantum circuits under a practical restriction

  • Author

    Yamashita, S. ; Minato, S.-i. ; Michael, M.D.

  • Author_Institution
    Nara Inst. of Sci. & Technol., Nara
  • fYear
    2008
  • fDate
    8-11 July 2008
  • Firstpage
    873
  • Lastpage
    879
  • Abstract
    Recently much attentions have been paid to quantum circuit design to prepare for the future ldquoquantum computation era.rdquo Like the conventional logic synthesis, it should be important to verify and analyze the functionalities of generated quantum circuits. For that purpose, we propose an efficient verification method for quantum circuits under a practical restriction. Thanks to the restriction, we can introduce an efficient verification scheme based on decision diagrams called Decision Diagrams for Matrix Functions (DDMFs). Then, we show analytically the advantages of our approach based on DDMFs over the previous verification techniques. In order to introduce DDMFs, we also introduce new concepts, quantum functions and matrix functions, which may also be interesting and useful on their own for designing quantum circuits.
  • Keywords
    decision diagrams; functions; logic design; logic testing; matrix algebra; quantum gates; decision diagram; logic synthesis; matrix function; quantum circuit design; quantum circuit verification; quantum computation; quantum function; quantum gate; Boolean functions; Circuit synthesis; Data structures; Integrated circuit modeling; Logic gates; Matrix decomposition; Quantum computing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer and Information Technology, 2008. CIT 2008. 8th IEEE International Conference on
  • Conference_Location
    Sydney, NSW
  • Print_ISBN
    978-1-4244-2357-6
  • Type

    conf

  • DOI
    10.1109/CIT.2008.4594789
  • Filename
    4594789