Implementation of FPGA-based DVB-T2 modulator with multiple PLPs

Digital Video Broadcasting - Terrestrial for Second generation (DVB-T2) was released, for the purpose of supporting High Definition Television (HDTV) services. Although DVB-T2 leads to performance improvement by introducing state-of-the-art communication techniques, the introduction of such communication techniques has become problems in implementing the system. Multiple Physical Layer Pipe (PLP), initially introduced by DVB-T2, enable application of separate code rates and modulation orders to each PLP. However, due to non-sequentially generated Base Band (BB) frames, regardless of PLP indices, construction of T2 frames is complicated. In the present paper, we present an algorithm arranging randomly produced BB frames to build T2 frames, complying with the DVB-T2 standard. The proposed method is centered on allocating memory space to each PLP, based on configurable PLP information and storing BB frames in an external memory. In addition to such an algorithm, DVB-T2 modulator is implemented in a Field Programmable Gate Array (FPGA) device.