• DocumentCode
    2510086
  • Title

    On buffering schemes for long multi-layer nets

  • Author

    Prasad, Vani ; Desai, Madhav P.

  • Author_Institution
    Dept. of Electr. Eng., Indian Inst. of Technol., Mumbai, India
  • fYear
    2004
  • fDate
    2004
  • Firstpage
    455
  • Lastpage
    460
  • Abstract
    We consider the problem of minimizing the delay in signal transmission over point-to-point connections across multiple metal layers in a VLSI circuit. We present an exact solution for the two layer case. This exact solution, however, is irregular and dependent on the length of the net. We look for approximate solutions which are not only regular but are independent of the length of the net. We show that two of these approximate solutions yield delays that are within a constant of the optimal solution. We have seen that our results hold true even for the three-layer case. We conjecture that our models can be inductively extended for multi-layer nets as well.
  • Keywords
    VLSI; buffer circuits; circuit optimisation; delays; VLSI circuit; buffering; delays; minimization; multilayer nets; multiple metal layers; signal transmission; very large scale integrated circuit; Capacitance; Delay; Integrated circuit interconnections; Logic; Minimization; Process design; Routing; System performance; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2004. Proceedings. 17th International Conference on
  • Print_ISBN
    0-7695-2072-3
  • Type

    conf

  • DOI
    10.1109/ICVD.2004.1260964
  • Filename
    1260964