DocumentCode :
2510125
Title :
Untestable fault identification using recurrence relations and impossible value assignments
Author :
Syal, Manan ; Hsiao, Michael S.
Author_Institution :
Bradley Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA, USA
fYear :
2004
fDate :
2004
Firstpage :
481
Lastpage :
486
Abstract :
This paper presents two novel and low cost techniques that can be used for the purpose of untestable fault identification. First, we present a new theorem and a practical method using static implications to identify unexcitable nets using recurrence relations in sequential circuits. Since each unexcitable net generally infers to more than one untestable fault, this theorem helps us to quickly identify significantly more sequentially untestable faults. In addition to discovering unexcitable nets using recurrence relations, we propose a second approach that aims at quickly identifying non-trivial multiple-node conflicts, which can then be used to identify additional untestable faults in both combinational and sequential circuits. Unlike previous techniques that concentrate on identifying local conflicts in the circuit, our approach efficiently extends the conflicting value analysis across multiple levels in the circuit to identify more untestable faults. Application of our techniques to both combinational and sequential benchmark circuits showed that significantly more untestable faults can be identified using the proposed approaches, with low overhead in terms of both memory and execution time.
Keywords :
benchmark testing; combinational circuits; fault diagnosis; sequential circuits; combinational benchmark circuits; combinational circuits; execution time; impossible value assignments; nontrivial multiple node conflicts; recurrence relations; sequential benchmark circuits; unexcitable nets identification; untestable fault identification; Automatic test pattern generation; Circuit faults; Circuit testing; Electrical fault detection; Engines; Fault detection; Fault diagnosis; Fires; Sequential circuits; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN :
0-7695-2072-3
Type :
conf
DOI :
10.1109/ICVD.2004.1260967
Filename :
1260967
Link To Document :
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