DocumentCode
2510178
Title
A linked list cache coherence protocol: verifying the bottom layer
Author
Gjessing, Stein ; Krogdahl, Stein ; Munthe-Kaas, Ellen
Author_Institution
Dept. of Inf., Oslo Univ., Norway
fYear
1991
fDate
30 Apr-2 May 1991
Firstpage
324
Lastpage
329
Abstract
High performance and correctness are crucially important in hardware development. This paper discusses aspects of correctness of a linked list cache coherence protocol. The protocol is tailored to execute as many operations as possible in parallel, achieving speed and avoiding the memory bottleneck. This makes it hard to verify that the protocol is correct. In the paper, a bottom layer of the protocol is identified and it is shown how the correctness of this layer can be established
Keywords
buffer storage; data structures; parallel processing; performance evaluation; protocols; bottom layer verification; correctness; linked list cache coherence protocol; memory bottleneck; Data structures; Hardware; Informatics; Protocols;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing Symposium, 1991. Proceedings., Fifth International
Conference_Location
Anaheim, CA
Print_ISBN
0-8186-9167-0
Type
conf
DOI
10.1109/IPPS.1991.153798
Filename
153798
Link To Document