The third generation verification technology based SOC debugging

Co-verification technologies are characterized by two inherently conflicting issues: signal observability and simulation performance. To overcome these limitations, we proposed a run-time RTL debugging methodology for FPGA-based co-simulation as well as debugging methodology for a FPGA emulator with testbench synthesis engine. The first method provides internal nodes probing on an event-driven co-simulation platform and achieves full observability for DUT with better simulation performance. In the second method, the proposed testbench synthesis engine is built by hardware constructs in terms of Verilog IEEE Simulation Model to correspond with the testbench. Internal nodes are hardware-wired to DUT top-level during compilation, then sampled continuously by a sample logic into on-chip storage device (e.g. Block RAM, SDRAM and etc). Thus better observability can be achieved without stopping of DUT clock.