LVDS driver design for high speed serial link in 0.13um CMOS technology

Author

Zongxiong, Yang ; Xiaohua, Lv ; Huihua, Liu ; Lei, Li ; Wanting, Zhou

Author_Institution

Space IC R&D Center, UESTC, Chengdu, China

fYear

2011

fDate

21-23 Oct. 2011

Firstpage

145

Lastpage

148

Abstract

This paper presents a LVDS (low voltage differential signal) driver, which works at 2 Gbps, with a pre-emphasis circuit compensating the attenuation of limited bandwidth of channel. To make the output common-mode (CM) voltage stable over process, temperature, and supply voltage variations, a closed-loop negative feedback circuit is added in this work. The LVDS driver is designed in 0.13 um CMOS technology using both thick (3.3 V) and thin (1.2 V) gate oxide device, simulated with transmission line model and package parasitic model. The simulated results show that this driver can operate up to 2 Gbps with random data patterns.

Keywords

CMOS integrated circuits; circuit feedback; driver circuits; high-speed integrated circuits; integrated circuit design; low-power electronics; CMOS technology; LVDS driver design; bit rate 2 Gbit/s; channel bandwidth; closed loop negative feedback circuit; high speed serial link; low voltage differential signal driver; output common mode voltage; package parasitic model; preemphasis circuit; random data pattern; size 0.13 mum; supply voltage variation; thick gate oxide device; thin gate oxide device; transmission line model; voltage 1.2 V; voltage 3.3 V; Integrated circuit modeling; Power demand; Power transmission lines; Resistors; Simulation; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Computational Problem-Solving (ICCP), 2011 International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4577-0602-8

Electronic_ISBN

978-1-4577-0601-1

Type

conf

DOI

10.1109/ICCPS.2011.6092214

Filename

6092214