Title :
A novel 2.5bit SHA-less MDAC design for 10bit 100Ms pipeline ADC
Author :
Su, Yingping ; Ning, Ning ; Yu, Qi
Author_Institution :
Lab. of Mixed & Analog Circuit Design, Univ. of Electron. Sci. & Technol., Chengdu, China
Abstract :
A sub circuit block - 2.5bit MDAC used in 10 bit 100MHz pipeline ADC fabricated in TSMC 0.35um process is presented in this paper. The pipeline ADC removes a front Sample and Hold block (SH) to save power dissipation and area. However, the aperture error between the multiplying digital-to-analog converter (MDAC) and the comparators in the sub flash may increases in large amount. It obviously decreases the precision of sample phase. In this paper, there are two ways to decrease the aperture error. Furthermore, in order to improve the accuracy of sample signal, a simplified boost-strapped switch is adopted in first 2.5bit SHA-less MDAC design, which only uses one capacitor to restore the adding voltage. The result shows that the MDAC consume 30.73 mW under 3.3v power supply. The settling time is 3ns for input signal at Nyquist rate of 50mHz.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; capacitors; comparators (circuits); digital-analogue conversion; integrated circuit design; multiplying circuits; pipeline processing; power aware computing; Nyquist rate; SHA-less MDAC design; TSMC process; aperture error; booststrapped switch; capacitor; comparators; multiplying digital-to-analog converter; pipelined ADC; power dissipation saving; sample and hold block; settling time; size 0.35 mum; subcircuit block; voltage 3.3 V; word length 10 bit; word length 2.5 bit; Gain; Latches; Pipelines; Signal resolution; Simulation; Switches; Transfer functions; MDAC; Pipeline ADC; SHA-less; boost-strapped switch;
Conference_Titel :
Computational Problem-Solving (ICCP), 2011 International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4577-0602-8
Electronic_ISBN :
978-1-4577-0601-1
DOI :
10.1109/ICCPS.2011.6092216
