Analytical expressions for static characteristics of submicron CMOS inverters

In this paper we derive analytical & physical based expressions to characterize the static behavior of the submicron CMOS inverter. The model expressions include formulae to estimate the logic threshold voltage and noise margins of submicron CMOS inverters. These expressions have been derived from a small geometry physics based model borrowed from due to its simple mathematical form, high accuracy to plot the I-V characteristics of MOSFETs right up to 0.1 μ, inclusion of small geometry effects like DIBL, channel length modulation, velocity saturation mobility degradation, etc and its physical basis. These expression shows an error of 5% on an average when benchmarked against numerical models like BSIM 3.