Analog VLSI architecture for discrete cosine transform using dynamic switched capacitors

This paper describes an analog VLSI architecture, to compute discrete cosine transform (DCT), using switched-switched capacitor blocks. The scheme operates from the general expression of DCT where input samples are multiplied by all the DCT coefficients simultaneously using an array of capacitors. These multiplied values are then switched parallely with the help of a cross-point switch, to different integrators to perform multiplication and accumulation(MAC). It can be used to compute DHT,DST and DFT and also its inverses. Proposed architecture is very simple to implement and suitable where silicon area and power issues are important with some compromise on accuracy.