Cross Layer Hardware Demonstrator for Wireless Communication Based on a FPGA

Author

Georgi, Sebastian ; Prieske, Christian ; Rohling, Hermann

Author_Institution

Inst. of Telecommun., Hamburg Univ. of Technol., Hamburg, Germany

fYear

2009

fDate

25-27 Sept. 2009

Firstpage

9

Lastpage

13

Abstract

This paper describes a hardware demonstrator for wireless communication applications which is integrated into a single FPGA. The physical layer (PHY) is based on the Orthogonal Frequency Division Multiplexing (OFDM) transmission technique and is implemented with dedicated logic. The data link layer is defined by program code which is executed on the LEON3, a RISC processor module which is based on the SPARC architecture.

Keywords

OFDM modulation; field programmable gate arrays; microprocessor chips; radiocommunication; reduced instruction set computing; FPGA; OFDM transmission technique; RISC processor module; SPARC architecture; cross layer hardware demonstrator; data link layer; orthogonal frequency division multiplexing; physical layer; program code; wireless communication; Baseband; Cross layer design; Embedded computing; Field programmable gate arrays; Hardware; Media Access Protocol; OFDM; Physical layer; Telecommunication computing; Wireless communication; DLL; FPGA Prototyping; Hardware Complexity; MAC; OFDM;

fLanguage

English

Publisher

ieee

Conference_Titel

Scalable Computing and Communications; Eighth International Conference on Embedded Computing, 2009. SCALCOM-EMBEDDEDCOM'09. International Conference on

Conference_Location

Dalian

Print_ISBN

978-0-7695-3825-9

Type

conf

DOI

10.1109/EmbeddedCom-ScalCom.2009.12

Filename

5341580