DocumentCode :
2510789
Title :
Game theoretic modeling of voltage and frequency scaling during behavioral synthesis
Author :
Murugavel, Ashok K. ; Ranganathan, N.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
fYear :
2004
fDate :
2004
Firstpage :
670
Lastpage :
673
Abstract :
Frequency scaling has recently become an important area for exploration with respect to power and energy optimization. In this work, we describe a new methodology for simultaneous voltage and frequency scaling during scheduling in behavioral synthesis based on game theory for power and energy reduction. The problem of scheduling in synthesis is formulated as an auction based non-cooperative finite game, for which solutions are developed based on the Nash equilibrium function. Each operation in the data-path is modeled as a player bidding for executing an operation in the given control cycle, with the estimated power consumption as the bid. We develop game theoretic models and propose a resource constrained algorithm. Experimental results on selected benchmark circuits show that the proposed algorithm yields about 42.5% energy savings on the average.
Keywords :
game theory; high level synthesis; low-power electronics; optimisation; power consumption; scheduling; Nash equilibrium function; auction theoretic model; behavioural synthesis; benchmark circuits; data-path; energy reduction; frequency scaling; game theoretic modeling; noncooperative finite game; power reduction; resource constrained algorithm; scheduling; voltage scaling; Capacitance; Circuits; Clocks; Dynamic voltage scaling; Energy consumption; Frequency synthesizers; Game theory; Nash equilibrium; Processor scheduling; Scheduling algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN :
0-7695-2072-3
Type :
conf
DOI :
10.1109/ICVD.2004.1261000
Filename :
1261000
Link To Document :
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