DocumentCode
2511391
Title
Bounds on performance of VLSI processor arrays
Author
Nayak, Amiya ; Santoro, Nicola
Author_Institution
Center for Parallel & Distributed Comput., Carleton Univ., Ottawa, Ont., Canada
fYear
1991
fDate
30 Apr-2 May 1991
Firstpage
364
Lastpage
370
Abstract
This paper discusses the effect of processor failures on computation performed on two-dimensional VLSI processor arrays. Previously established properties of catastrophic fault patterns are used to study inherent limits to reconfigurability of these regular architectures. Bounds on number of faults the system can tolerate to provide guaranteed performance are derived. These results are the generalization of the results obtained in the case of one-dimensional processor arrays
Keywords
VLSI; fault tolerant computing; parallel processing; VLSI processor arrays; bounds on performance; catastrophic fault patterns; inherent limits; one-dimensional processor arrays; processor failures; reconfigurability; Circuit faults; Computer architecture; Computer science; Distributed computing; Fault detection; Fault tolerance; Fault tolerant systems; Joining processes; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing Symposium, 1991. Proceedings., Fifth International
Conference_Location
Anaheim, CA
Print_ISBN
0-8186-9167-0
Type
conf
DOI
10.1109/IPPS.1991.153804
Filename
153804
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