ESD protection for the deep sub micron regime - a challenge for design methodology

ESD protection has been an inevitable component of integrated circuits since the invention of semiconductor devices. A huge number of concepts and protection devices have been designed and optimized for this purpose by ESD engineers. Even it seems to be a simple functionality just to shunt a discharge current during an ESD event, almost each step in the shrinking path needs new adjustment of the protection circuits and sometimes even implementation of totally new concepts. Entering the sub 100 nm regime the protection development goes much beyond the development of a specific optimized protection element. A sophisticated protection network has to be designed which covers both the IO circuit and the core region, where low oxides thickness and low junction breakdown voltages lead to hard constraints on the maximum voltage overshoot during ESD. In especially designs with multiple power supply domains will complicate the ESD supply protection concept extremely. To achieve a good ESD robustness it will be necessary to consider the ESD protection as integral part of the IC development starting from the concept phase. To support this and to extract the necessary data for an ESD optimization an IC level ESD simulation approach is presented which analyses the critical discharge paths across the chip.